Liquid crystal display devices utilizing amorphous silicon thin film transistors (hereinafter referred to as “a-Si TFTs”) as driver elements have conventionally been known. In recent years, development of liquid crystal display devices utilizing microcrystalline silicon thin film transistors (hereinafter referred to as “μc-Si TFTs”) as driver elements is moving forward. Mobility of microcrystalline silicon is greater than that of amorphous silicon, and the μc-Si TFTs can be formed by a process similar to that of the a-Si TFTs. For this reason, employment of the μc-Si TFTs as the driver elements is expected to realize such as a cost reduction by decreasing a frame area, a cost reduction by decreasing a number of chips in a driver IC, an improvement of a mounting yield, and an increase in size of display devices. Further, the μc-Si TFTs have a characteristic that a threshold shift (a change in a threshold voltage) when a voltage is applied to a gate electrode for an extended period of time is smaller than that of the a-Si TFTs. In other words, the μc-Si TFTs are more reliable than the a-Si TFTs in that the μc-Si TFTs are insusceptible to degradation.
By the way, a display unit of an active matrix-type liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines (scanning signal lines), and a plurality of pixel formation portions respectively provided at intersections of the plurality of source bus lines and the plurality of gate bus lines. These pixel formation portions are arranged in a matrix to constitute a pixel array. Each pixel formation portion includes such as a thin film transistor as a switching element whose gate terminal is connected to the gate bus line that passes the corresponding intersection and whose source terminal is connected to the source bus line that passes the corresponding intersection, and a pixel capacitance for storing a pixel value. Further, such an active matrix-type liquid crystal display device is provided with a source driver (video signal line drive circuit) for driving the plurality of source bus lines and a gate driver (scanning signal line drive circuit) for driving the plurality of gate bus lines.
Video signals indicating pixel values are transferred via the source bus lines. However, it is not possible to transfer video signals indicating pixel values for the plurality of lines at one time (the same time) through a single source bus line. For this reason, the video signals are written to the pixel capacitances in the pixel formation portions arranged in a matrix sequentially line by line. Therefore, the gate driver is configured by a shift register having a plurality of stages so that the plurality of gate bus lines are sequentially selected for a predetermined period.
FIG. 28 is a circuit diagram illustrating a configurational example of a single stage of a shift register included in the conventional gate driver. The circuit includes thin film transistors MA, MB, MD, ME, ML, MN, and MI, and a capacitor Cap1. A source terminal of the thin film transistor MB, a drain terminal of the thin film transistor MA, a drain terminal of the thin film transistor ME, a drain terminal of the thin film transistor ML, a gate terminal of the thin film transistor MI, and one end of the capacitor Cap1 are connected to each other via a range (wiring) netA. An output terminal 96 connected to the gate bus line is connected to a drain terminal of the thin film transistor MI. In the above configuration, the netA is precharged by supplying a pulse of a start signal S to an input terminal 92. When a potential of a clock CKA changes from a low level to a high level in this state, as a parasitic capacitance (not shown) occurs between the gate and source of the thin film transistor MI, a potential of the netA increases via the parasitic capacitance. This turns the thin film transistor MI to an ON state, increases a potential of the output terminal 96, and turns the gate bus line connected to this output terminal 96 to a selected state. Such an operation is sequentially carried out in each of the stages that configure the shift register, and whereby the plurality of gate bus lines are sequentially turned to the selected state and the video signals are written to the pixel capacitances line by line.
Further, Japanese Unexamined Patent Application Publication No. 2006-351171 discloses a circuit diagram as a configuration of a single stage of a shift register as shown in FIG. 29. According to this configuration, an effect of a parasitic capacitance can be minimized and a stable gate output can be generated. Moreover, Japanese Unexamined Patent Application Publication No. 2006-190437 discloses an invention relating to a shift register capable of preventing a malfunction due to degradation of a thin film transistor from occurring.